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February 2001
GENERAL DESCRIPTION
The HI-8482 bus interface unit is a silicon gate CMOS device designed as a dual differential line receiver in accordance with the requirements of the ARINC 429 bus specification. The device translates incoming ARINC 429 signals to normal CMOS/TTL levels on each of its two independent receive channels. The HI-8482 is also functionally equivalent to the Fairchild/Raytheon RM3183. The self-test inputs force the outputs to either a ZERO, ONE, or NULL state for system tests. While in self-test mode, the ARINC inputs are ignored. All the ARINC inputs have built-in hysteresis to reject noise that may be present on the ARINC bus. Additional input noise filtering can also be accomplished with external capacitors. The HI-8482 line receiver is one of several options offered by Holt Integrated Circuits to interface to the ARINC bus. The digital data processing for serial-to-parallel conversion and clock recovery can be accomplished with the HI-6010, HI-8683 or similar devices. The HI-8482 is available in a variety of ceramic & plastic packages including Small Outline (SOIC), J-Lead PLCC, Cerquad, DIP & Leadless Chip Carrier (LCC).
PIN CONFIGURATIONS (Top Views)
IN2B - 4 OUT2B - 5 IN2A - 6 CAP2A - 7 OUT2A - 8
HI-8482J HI-8482JT
20 - PIN PLASTIC J-LEAD PLCC
18 - IN1A 17 - CAP1B 16 - IN1B 15 - OUT1A 14 - GND
FEATURES
! Converts ARINC 429 levels to digital data ! Direct replacement for the RM3183 ! Greater than 2 volt receiving hysteresis ! TTL and CMOS outputs and test inputs ! Military screening available ! 20-Pin SOIC, PLCC, CERQUAD. DIP & LCC packages are available
-VS - 1 TESTA - 2 CAP2B - 3 IN2B - 4 OUT2B - 5 IN2A - 6 CAP2A - 7 OUT2A - 8 +VL - 9 N/C - 10
HI-8482PSI HI-8482PST
20 - PIN PLASTIC SMALL OUTLINE (SOIC) - WB
20 - TESTB 19 - CAP1A 18 - IN1A 17 - CAP1B 16 - IN1B 15 - OUT1A 14 - GND 13 - N/C 12 - OUT1B 11 - +VS
TRUTH TABLE
ARINC INPUTS V (A) - V (B)
Null Zero One Don't Care Don't Care Don't Care
TEST INPUTS TEST A
0 0 0 0 1 1
OUTPUTS OUT A
0 0 1 0 1 0
TEST B
0 0 0 1 0 1
OUT B
0 1 0 1 0 0
(DS8482 Rev. C)
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02/01
HI-8482
FUNCTIONAL DESCRIPTION
The HI-8482 contains two independent ARINC 429 receive channels. The diagram in Figure 1 illustrates a typical HI8482 receive channel. The differential ARINC signal input is converted to a positive signal referenced to ground through level shifters and a unity gain differential amplifier. A positive differential input signal is converted to a positive signal on the plus output of the differential amplifier. This output is proportional in amplitude to the original input signal. At the same time, the corresponding MINUS output is pulled to GND. Likewise when a negative input signal is present at the ARINC inputs, a positive signal is present on the MINUS output and the PLUS output is pulled to GND. The outputs of the differential amplifier are compared with the ONE, ZERO and NULL threshold levels to produce the appropriate logic level on the OUTA and OUTB outputs of the device. The ARINC clock signal may be recovered through a NOR function of OUTA and OUTB. The test inputs logically disconnect the outputs of the comparators from OUTA and OUTB and force the device outputs to one of the three valid states (Figure 5). This alleviates having to ground the ARINC inputs during test mode operation. ARINC LEVELS The ARINC 429 specification requires the following detection levels: STATE ONE NULL ZERO DIFFERENTIAL VOLTAGE +6.5V to +13V +2.5V to -2.5V -6.5V to -13V
The HI-8482 guarantees recognition of these levels with a common mode voltage with respect to GND less than 5V for the worst case condition. NOISE The input hysteresis is set to reject voltage level transitions in the undefined region between the maximum ZERO level and the minimum NULL level and the undefined region between the maximum NULL level and the minimum ONE level. Therefore, once a valid input differential voltage threshold is detected, the outputs will remain at a valid logic state until a new valid input voltage is detected. In addition to the hysteresis, the CapA and CapB pinsmake it possible to add simple RC filters to the ARINC inputs.
TESTA TESTB INA CAPA INB CAPB LEVEL SHIFT
DIFF AMP
LEVEL SHIFT
Detect Level Comp Comparators w / hysteresis Comp Detect Level
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HI-8482
ground (GND) connection should be sturdy and isolated from large switching currents to provide a quiet ground reference. The HI-8482 can be used with HI-8382 or HI-8585 Line Drivers to provide a complete analog ARINC 429 interface solution. A simple application, which can be used in systems requiring a repeater type circuit for long transmissions or for test interfaces, is given in Figure 3. More HI-8382 or HI-8585 drivers may be added to test multiple ARINC channels, as shown.
TYPICAL APPLICATIONS
APPLICATIONS
The standard connections for the HI-8482 are shown in Figure 2. Decoupling of the supply should be done near the IC to avoid propagation of noise spikes due to switching transients. The
ARINC RECEIVER STANDARD CONNECTIONS
+5V +15V
HI-8482
ARINC CHANNEL 1
39 pF
IN1A IN1B CAP1A
39 pF
OUT1A OUT1B
A B
CHANNEL 1 DATA OUT TO LOGIC
CAP1B IN2A IN2B OUT2A OUT2B A B CHANNEL 2 DATA OUT TO LOGIC
ARINC CHANNEL 2
39 pF 39 pF
CAP2A CAP2B TESTA N/C TESTB N/C
LOGIC TEST INPUTS
-15V
ARINC REPEATER CIRCUIT
ARINC INPUT CHANNEL
IN1A IN1B OUT1A OUT1B DATA (A) DATA (B) AOUT BOUT
A B
ARINC OUTPUT CHANNEL 1
DATA (A) DATA (B)
AOUT BOUT
A B
ARINC OUTPUT CHANNEL 2
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HI-8482
PIN DESCRIPTION TABLE
SYMBOL FUNCTION CAP1A CAP1B CAP2A CAP2B GND IN1A IN1B IN2A INPUT INPUT INPUT INPUT POWER INPUT INPUT INPUT DESCRIPTION Filter capacitor input for terminal A of channel 1 Filter capacitor input for terminal B of channel 1 Filter capacitor input for terminal A of channel 2 Filter capacitor input for terminal B of channel 2 0 Volts ARINC input terminal A of channel 1 ARINC input terminal B of channel 1 ARINC input terminal A of channel 2 SYMBOL FUNCTION IN2B OUT1A OUT1B OUT2A OUT2B TESTA TESTB +VL +Vs -Vs INPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT POWER POWER POWER DESCRIPTION ARINC input terminal B of channel 2 TTL output terminal A of channel 1 TTL output terminal B of channel 1 TTL output terminal A of channel 2 TTL output terminal B of channel 2 Test input terminal A Test input terminal B +5 Volts 10% +12 Volts 10% or +15 Volts 10% -12 Volts 10% or -15 Volts 10%
TIMING DIAGRAMS
+10V ARINC
DIFFERENTIAL INPUT
0V -10V
tPLH
50%
tr
90% 10%
tf
OUTA
tPHL
tPLH
tPHL
50%
OUTB
FIGURE 4.
+5V TESTA 0V +5V TESTB 0V
tTLH
50%
tr
90% 10%
tf
OUTA (test)
tTHL
tTLH
tTHL
50%
OUTB (test)
FIGURE 5.
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HI-8482
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to Gnd = 0V)
Supply Voltage, +VS:......................................................................+20 VDC -VS: .......................................................................-20 VDC +VL:........................................................................+7 VDC Operating Temperature Range: (Industrial) .........................-40C to +85C (Hi-Temp) ........................-55C to +125C (Military) ..........................-55C to +125C Internal Power Dissipation: ..............................................................900mW Voltage at ARINC Inputs: .......................................................-29V to +29V Voltage at Any Other Input:.............................................-0.3V to VL + 0.3V Output Short Circuit Protected: .............................................Not Protected Storage Temperature Range: .........................................-65C to +150C Soldering Temperature: (Ceramic).................................30 sec. at +300C (Plastic - leads)........................10 sec. at +280C (Plastic - body) ................................+220C Max.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
12 < VS < 15, VL = +5V, Operating temperature range (unless otherwise noted)
PARAMETERS ARINC inputs - IN1A, IN1B, IN2A, IN2B V(A) - V(B) V(A) - V(B) V(A) - V(B) (|V(A)| - |V(B)|) / 2 Input resistance - input A to input B Input resistance - input A or B to Gnd Input capacitance - input A to B Input capacitance - input A or B to Gnd Tes t inputs - TESTA, TESTB Logic 1 input voltage Logic 0 input voltage Logic 1 input current (magnitude) Logic 0 input current Outputs - OUT1A, OUT1B, OUT2A, OUT2B Voltage - sourcing 100A Voltage - sourcing 2.8mA Voltage - sinking 100A Voltage - sinking 2.0mA Rise time Fall time Propagation delay - low to high (ARINC) Propagation delay - high to low (ARINC) Propagation delay - low to high (TESTA/B) Propagation delay - low to high (TESTA/B) Supply current +VS current +VS current -VS current -VS current +VL current +VL current SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VIH VIL VNULL VCM RI RG CI CG
OUTA = 1 OUTB = 1 OUTA = OUTB = 0 Frequency = 80KHz Supply pins floating Supply pins floating Filter caps disconnected Filter caps disconnected
6.5 -6.5 -2.5 30K 19K see note 1 see note 1
10 -10 0 5 50K 25K 5 5
13 -13 2.5
10 10
volts volts volts volts ohms ohms pF pF
VIH VIL IIH IIL
ARINC inputs to Gnd ARINC inputs to Gnd VIH = 2.7V VIL = 0V
2.7 5 0.5 0.8 15 1
volts volts A A
VOH VOH VOL VOL tr tf tPLH tPHL tTLH tTHL
TA = 25C Full temperature range TA = 25C Full temperature range CL = 50pF, TA = 25C CL = 50pF, TA = 25C CL = 50pF, TA = 25C and filter caps disconnected CL = 50pF, TA = 25C and filter caps disconnected CL = 50pF, TA = 25C CL = 50pF, TA = 25C
4 3.5 0.08 0.8 70 70
40 30 600 600 50 50
volts volts volts volts ns ns ns ns ns ns
IDD IDD IEE IEE ICC ICC
VS VS VS VS VS VS
= = = = = =
15V, 12V, 15V, 12V, 15V, 12V,
TA =25C, TESTA and TESTB = 0V TA =25C, TESTA and TESTB = 0V TA =25C, TESTA and TESTB = 0V TA =25C, TESTA and TESTB = 0V TA =25C, TESTA and TESTB = 0V TA =25C, TESTA and TESTB = 0V
3.7 3 8.7 7.4 9 8.6
7 6 15 14 20 18
mA mA mA mA mA mA
Notes:
1. Guaranteed by design.
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HI-8482
ADDITIONAL HI-8482 PIN CONFIGURATIONS
(All 20-Pin Package Configurations)
IN2B OUT2B IN2A CAP2A OUT2A
-
4 5 6 7 8
HI-8482U HI-8482UT
20-PIN J-LEAD CERQUAD
18 17 16 15 14
-
IN1A CAP1B IN1B OUT1A GND
IN2B OUT2B IN2A CAP2A OUT2A
-
4 5 6 7 8
HI-8482S HI-8482ST HI-8482SM-01
20-PIN CERAMIC LCC
18 17 16 15 14
-
IN1A CAP1B IN1B OUT1A GND
-VS - 1 TESTA - 2 CAP2B - 3 IN2B - 4 OUT2B - 5 IN2A - 6 CAP2A - 7 OUT2A - 8 +VL - 9 N/C - 10
20 - TESTB 19 - CAP1A
-VS - 1 TESTA - 2 CAP2B - 3 IN2B - 4 OUT2B - 5 IN2A - 6 CAP2A - 7 OUT2A - 8 +VL - 9 N/C - 10
20 - TESTB 19 - CAP1A 18 - IN1A
HI-8482C HI-8482CT HI-8482CM-01
20-PIN CERAMIC SIDE-BRAZED DIP
18 - IN1A 17 - CAP1B 16 - IN1B 15 - OUT1A 14 - GND 13 - N/C 12 - OUT1B 11 - +VS
HI-8482D HI-8482DT
20-PIN CERDIP
17 - CAP1B 16 - IN1B 15 - OUT1A 14 - GND 13 - N/C 12 - OUT1B 11 - +VS
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HI-8482
THERMAL CHARACTERISTICS
PACKAGE DESCRIPTION
PLASTIC SMALL OUTLINE (SOIC) PLASTIC J-LEAD PLCC CERDIP CERAMIC SIDE-BRAZED DIP CERAMIC J-LEAD CERQUAD CERAMIC LCC
THERMAL RESISTANCE JC
17C/W 30C/W 28C/W 28C/W 25C/W 25C/W
JA
90C/W 85C/W 90C/W 95C/W 95C/W 85C/W
ORDERING INFORMATION
PART NUMBER HI-8482C HI-8482CT HI-8482D HI-8482DT HI-8482J HI-8482JT HI-8482PSI HI-8482PST HI-8482S HI-8482ST HI-8482U HI-8482UT PACKAGE DESCRIPTION 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN CERDIP 20 PIN CERDIP 20 PIN PLASTIC J -LEAD PLCC 20 PIN PLASTIC J -LEAD PLCC 20 PIN PLASTIC SMALL OUTLINE (SOIC) 20 PIN PLASTIC SMALL OUTLINE (SOIC) 20 PIN CERAMIC LEADLESS CHIP CARRIER 20 PIN CERAMIC LEADLESS CHIP CARRIER 20 PIN J-LEAD CERQUAD 20 PIN J-LEAD CERQUAD TEMPERATURE RANGE -40C TO +85C -55C TO +125C -55C TO +125C -40C TO +85C -55C TO +125C -40C TO +85C -55C TO +125C -40C TO +85C -55C TO +125C -40C TO +85C -55C TO +125C -55C TO +125C -40C TO +85C -55C TO +125C FLOW I T M I T I T I T I T M I T BURN LEAD IN FINISH NO NO NO NO NO NO NO NO NO NO NO NO GOLD GOLD SOLDER SOLDER SOLDER SOLDER SOLDER SOLDER GOLD GOLD SOLDER SOLDER
HI-8482CM-01 20 PIN CERAMIC SIDE BRAZED DIP
YES SOLDER
HI-8482SM-01 20 PIN CERAMIC LEADLESS CHIP CARRIER
YES SOLDER
HOLT INTEGRATED CIRCUITS 7
HI-8482 PACKAGE DIMENSIONS
inches (millimeters)
20-PIN PLASTIC SMALL OUTLINE (SOIC) - WB (Wide Body)
Package Type: 20HW
.5035 .0075 (12.789 .191) .0105 .0015 (.2667 .0381) .4065 .0125 (10.325 .318) .296 .003 (7.518 .076) SEE DETAIL A .018 TYP (.457)
.090 .010 (2.286 .254)
0 to 8 .050 TYP (1.27) .033 .017 (.838 .432) DETAIL A
.0075 .0035 (.191 .089)
20-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 20C
1.000 .010 (25.400 .254) .310 .010 (7.874 .254) .050 TYP. (1.270 TYP.) .200 MAX. (5.080 MAX.) .085 .009 (2.159 .229)
.300 .010 (7.620 .254)
.125 MIN. (3.175 MIN.)
.017 .002 (.432 .051)
.100 .005 (2.540 .127)
.010 + .002/- .001 (.254 .051/-.025)
HOLT INTEGRATED CIRCUITS 8
HI-8482 PACKAGE DIMENSIONS
inches (millimeters)
20-PIN CERDIP
Package Type: 20D
1.060 MAX. (26.924 MAX.) .070 MAX. (1.778 MAX.)
.005 MIN. (.127 MIN.)
.288 .005 (7.315 .127)
.060 TYP. (1.524 TYP.)
.100 .010 (2.540 .254)
.310 .010 (7.874 .254)
.200 MAX. (5.080 MAX.)
.015 MIN. (.381 MIN.)
.170 MAX. (4.318 MAX.)
.125 MIN. (3.175 MIN.)
.018 .003 (.457 .760)
0 to 15
.010 .002 (.254 .051)
20-PIN PLASTIC PLCC
Package Type: 20J
PIN NO. 1 IDENT .045 x 45 .045 x 45 .050 .005 (1.27 .127)
.390 .005 (9.906 .127) SQ.
.353 .003 (8.966 .076) SQ.
.017 .004 (.432 .102)
SEE DETAIL A .173 .008 (4.394 .203) .310 .020 (7.874 .508)
.009 .011
.015 .002 (.381 .051) .020 MIN (.508 ) R .025 .045
DETAIL A
HOLT INTEGRATED CIRCUITS 9
HI-8482 PACKAGE DIMENSIONS
inches (millimeters)
20-PIN CERAMIC LEADLESS CHIP CARRIER
Package Type: 20S
.040 x 45 3 PLCS (1.016 x 45 3 PLCS) .020 INDEX (.508 INDEX) PIN 1
.080 .020 (2.032 .508) .075 .004 (1.905 .101) .009R .006 (.229R .152) .050 BSC (1.270 BSC)
.175 .004 (4.445 .101) PIN 1 .050 .005 (1.270 .127)
.350 .008 (8.890 .203) SQ.
.025 .003 (.635 .076)
20-PIN J-LEAD CERQUAD
Package Type: 20U
2 1 20 19
.405 MAX. (10.287) MAX. SQ.
.335 .010 (8.509 .254)
.375 .008 (9.525 .203) .190 MAX. (4.826) MAX. .040 TYP. (1.016) TYP. .019 .003 (.483 .076)
.050 TYP. (1.270) TYP.
HOLT INTEGRATED CIRCUITS 10

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